In FIGS. 1 and 2, a four-terminal JFET 10 is shown. Four-terminal JFETs are comprised of the following terminals: a substrate 14, a gate 11c, a first channel terminal 13c, and a second channel terminal 16c. Usually, the first channel terminal 13c is the source and the second channel terminal 16c is the drain. Typically the substrate 14 and the gate 11c will be made of a first conduction type, such as p, and are usually highly doped. The source 13c and drain 16c are usually made of a second conduction type, which is opposite of the conduction type of the gate 11c, such as n, and are also highly doped. The gate 11c and source 13c are usually embedded in an upper layer 15a-c that is the same conduction type as the source 13c, such as n, but is usually not highly doped. This upper layer 15a-c is often an epitaxial layer.
A gate pad 11a, used for making an external connection to the gate 11c, may be attached to the gate through a gate trace 11b. The gate pad 11a and/or gate trace 11b may be situated over, and electrically isolated from, the source 13c. An insulating material 12, such as an oxide may be used to isolate the source 13c from the gate pad 11a and/or gate trace 11b. Similarly, a source pad 13a is connected to the source 13c via a source trace 13b, and a drain pad 16a is connected to the drain 16c via a drain trace 16b. 
The upper layer 15a-c may be divided into three different sections. There may be no actual separation between the sections, but such a division may aid in description of the device. Section one 15c of the upper layer is the section that is disposed at least partly beneath the gate 11c. Section two 15a of the upper layer is the section that is disposed beneath the gate pad 11a. Section three 15b of the upper layer is the section that is disposed at least partly beneath the gate trace 11b. Section one 15c may also be disposed between the source 13c and the gate 11c, although the source 13c and the gate 11c may also touch each other with no such section between.
For optimal JFET performance, it is usually desirable to reduce the capacitance between the gate 11c and any other component because such capacitance can magnify undesirable noise in the device. The upper layer 15a-c may reduce the capacitance between the gate, gate trace, and gate pad 11a-c and the substrate 14. The insulating layer 12 may reduce the capacitance between the gate, gate trace, and gate pad 11a-c and the source 13c. Because the upper layer 15 is of the same conduction type as the source 13c, this upper layer is not very effective at reducing the capacitance between the source 13c and the gate pad 11a. 
As noted by dashed lines 17a-c, there are various capacitance paths between the gate, gate trace, and gate pad 11a-c and the source 13c. One capacitance path 17c is between the gate 13c and the source 11c. A second capacitance path 17b is between the gate trace 11b and the source 13c. Another capacitance path 17a is between the gate pad 11a and the source 13c. Because sections two and three 15a and 15b of the layer are electrically connected to the source 13c and because of the large size of the gate pad 11a, the capacitance through this path is significant. The combined capacitance of these three capacitance paths has a significant effect on noise amplification of the device. It would be beneficial to reduce this capacitance.